What is a NoC Interconnect?
Network-on-chip (NoC) interconnect technology is often called “a front-end solution to a back-end problem.” As semiconductor transistor dimensions shrink and increasing amounts of IP block functions are added to a chip, the physical infrastructure that carries data on the chip and guarantees quality of service begins to crumble. Many of today’s systems-on-chip are too complex to utilize a traditional hierarchal bus or crossbar interconnect approach. Yesterday’s village traffic has turned into today’s congested freeways.
Here are four reasons why today’s SoC’s need a NoC interconnect fabric:
- Reduce Wire Routing Congestion
- Ease Timing Closure
- Higher Operating Frequencies
- Change IP Easily
NoC Interconnect can be coherent or non-coherent, the concepts of coherent and non-coherent Network-on-Chip (NoC) interconnects are fundamental to understanding how data is managed and transferred across various components of the SoC. These concepts play a crucial role in optimizing performance, power efficiency, and ensuring data integrity across the system.
Reduce Wire Routing Congestion
Arteris’ NoC interconnect fabric technology significantly reduces the number of wires required to route data in a SoC, reducing routing congestion at the backend of the design process. Backend wire routing congestion has become one of the most significant factors causing late designs as the number of IP blocks on a SoC has increased.
Ease Timing Closure
The distributed architecture of Arteris network on chip interconnect fabrics allows for precise placement of pipelines (aka “register slices”) to easily resolve timing closure issues without affecting other areas of the chip.
Higher Operating Frequencies
NoC interconnects simplifies the hardware required for switching and routing functions, allowing SoCs with NoC interconnect fabrics to reach higher operating frequencies.
Furthermore, for long or speed-sensitive paths, the architect can easily place pipeline registers along any connection, allowing for higher frequencies. Precise placement of pipeline registers (also called “register slices”) allows the interconnect to exactly accommodate the SoC’s timing budget and meet its target frequency, with less pipeline register latency and no effect on neighboring IP block timing.
In addition to pipelining, distributed globally asynchronous locally synchronous (GALS) technology allows synchronous modules with locally generated clocks, with asynchronous connections between them.
In short, NoC technology’s simpler switching and routing hardware, fine granularity pipelining capability, and GALS allow NoC interconnects to achieve higher operating frequencies than inferior multi-layered bus or crossbar interconnects.
Easy Derivative Chips: Change IP Easily
Arteris NoC technology makes it easy to swap IP blocks to create derivative chips or to respond quickly to engineering change orders (ECOs) during development because Arteris NoC interconnects are protocol agnostic. In an Arteris NoC interconnect fabric, the transaction (protocol) layers are separate from the transport and physical layers. Small network interface units (NIUs) that convert IP protocol transaction into transport packets are synthesized close to initiator and target IP blocks, allowing the rest of the interconnect topology to be made of simpler IP blocks that perform switching and routing.
Ncore Cache Coherent Interconnect IP
A coherent NoC interconnect refers to a network infrastructure within an SoC that ensures cache coherence across the system. Cache coherence is a protocol that maintains consistency of data stored in local caches of various processors (or cores) in a multi-processor system. When multiple processors are accessing and modifying the same memory locations, a coherent NoC ensures that any changes made by one processor are immediately visible to all other processors, preventing data inconsistencies.
Key Features
- Cache Coherence Protocol: Ncore Implements the MOESI (Modified, Owned, Exclusive, Shared, Invalid) cache protocol to manage the states of data in caches and ensure consistency.
- Directory-Based or Snooping Mechanisms: Arteris Ncore coherent NoCs use directory-based mechanisms to track the state of shared data.
- Low Latency and High Bandwidth: Ncore is optimized for quick data transfer and synchronization across caches to minimize performance overhead due to coherence maintenance.
When to Use
- Multi-Core/Processor Systems: Essential in systems with multiple processing units that need to share data frequently and operate on shared memory models.
- Real-Time Applications: Where data consistency and quick access to shared data are crucial for system performance and predictability.
FlexNoC/FlexWay Non-Coherent NoC Interconnect
Non-coherent NoC interconnects, on the other hand, do not implement cache coherence protocols across the SoC. Each processor or core manages its local cache independently, without ensuring that data modifications are visible across the system. Non-coherent systems rely on software mechanisms to ensure data consistency when necessary, which can be less efficient but simpler and less power-consuming than hardware coherence mechanisms.
Key Features
- Simplicity and Lower Power: Less complex than coherent systems, leading to reduced power consumption and potentially simpler hardware design.
- Scalability for Specific Applications: Efficient for applications where data sharing among processors is minimal or can be efficiently managed through software.
When to Use
- Single-Core or Limited Inter-Core Communication Systems: Where the complexity and power consumption of coherence mechanisms do not justify their benefits.
- Systems with Predictable Data Sharing Patterns: Where software can efficiently manage data sharing and synchronization, minimizing the need for hardware coherence.
Combining Ncore Coherent and FlexNoC/FlexWay Non-Coherent NoCs for Optimal SoC Designs
Modern SoC designs combine both coherent and non-coherent NoC interconnects to leverage the strengths of each approach. For instance, a system might use a coherent NoC for the core processing cluster where high-performance and data consistency among cores are critical, while employing non-coherent interconnects for peripheral modules or specialized processing units where data sharing is minimal or can be managed at the software level.
Best Practices
- Hybrid Approaches: Our customers consider using coherent interconnects for critical data-sharing paths and non-coherent interconnects for less critical paths to optimize power and performance.
- Domain-Specific Architectures: Our customers often tailor the use of coherent and non-coherent interconnects based on the specific requirements of the application domain, such as multimedia processing, network processing, or real-time control systems.
By carefully selecting where and how to implement coherent and non-coherent NoC interconnects, designers can create SoCs that offer the best balance of performance, power efficiency, and scalability, tailored to the needs of their specific applications.
